Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs
Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs
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DOI：
10.1145/3350422
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发表时间：
2019-09
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影响因子：
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通讯作者：
Subodha Charles;Alif Ahmed;Ümit Y. Ogras;P. Mishra
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文献类型：
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作者：
Subodha Charles;Alif Ahmed;Ümit Y. Ogras;P. Mishra
动态缓存重新配置（DCR）是优化多核架构能耗的有效技术。虽然 DCR 的早期工作已经显示出有希望的节能机会，但现有技术并不适合多核架构，因为它们没有考虑内存、缓存和片上网络 (NoC) 流量之间的交互和紧密耦合。在本文中，我们提出了一种基于 NoC 的众核架构中的高效缓存重新配置框架。拟议的工作做出了三个主要贡献。首先，我们对基于分布式目录的众核架构进行建模，类似于 Intel Xeon Phi 架构。接下来，我们提出了一个高效的缓存重新配置框架，该框架考虑了所有重要组件，包括 NoC、缓存和主存。最后，我们提出了一种基于机器学习的框架，可以将探索时间减少一个数量级，而精度损失可以忽略不计。我们的实验结果表明，与基本缓存配置相比，平均节能 18.5%。
Dynamic cache reconfiguration (DCR) is an effective technique to optimize energy consumption in many-core architectures. While early work on DCR has shown promising energy saving opportunities, prior techniques are not suitable for many-core architectures since they do not consider the interactions and tight coupling between memory, caches, and network-on-chip (NoC) traffic. In this article, we propose an efficient cache reconfiguration framework in NoC-based many-core architectures. The proposed work makes three major contributions. First, we model a distributed directory based many-core architecture similar to Intel Xeon Phi architecture. Next, we propose an efficient cache reconfiguration framework that considers all significant components, including NoC, caches, and main memory. Finally, we propose a machine learning--based framework that can reduce the exploration time by an order of magnitude with negligible loss in accuracy. Our experimental results demonstrate 18.5% energy savings on average compared to base cache configuration.