A Surface Tailoring Method of Ultrathin Polymer Gate Dielectrics for Organic Transistors: Improved Device Performance and the Thermal Stability Thereof

A Surface Tailoring Method of Ultrathin Polymer Gate Dielectrics for Organic Transistors: Improved Device Performance and the Thermal Stability Thereof
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DOI:
10.1002/adfm.201500952
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发表时间:
2015-07
影响因子:
19
通讯作者:
Hyejeong Seong;Jieung Baek;Kwanyong Pak;S. Im
Hyejeong Seong;Jieung Baek;Kwanyong Pak;S. Im
中科院分区:
材料科学1区
文献类型:
--
作者:
Hyejeong Seong;Jieung Baek;Kwanyong Pak;S. Im

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调整介电层的表面对于与有机薄膜晶体管(OTFT)的后续沟道层形成良好界面至关重要。在这里,通过引发的化学气相沉积(iCVD)将简单的表面处理方法应用到基于有机硅的介电层(<15 nm)上,以使其与有机半导体兼容,而不会降低其绝缘性能。通过短暂的氧等离子体处理在15 nm厚的聚(1,3,5-三甲基-1,3,5-三乙烯基环三硅氧烷)(pV 3D 3)上形成分子薄氧化物覆盖层。覆盖层大大提高了陶瓷的热稳定性,而不会降低陶瓷原有的机械柔性和绝缘性能。此外,通过等离子体处理形成的表面硅烷醇官能团也可以用于用硅烷化合物进行表面改性。将表面改性的石墨烯应用于制造低电压操作(<5V)的基于并五苯的OTFT。具有表面处理的15 nm厚pV 3D 3的器件的最高场效应迁移率为0.59 cm 2 V−1 s−1,与具有原始pV 3D 3的TFT相比提高了两倍。据信,简单的表面处理方法可以广泛地扩展高度鲁棒性、可弯曲性和柔性的pV 3D 3栅极掩模的适用性,以设计掩模的表面,从而很好地匹配各种有机半导体。
Tailoring the surface of the dielectric layer is of critical importance to form a good interface with the following channel layer for organic thin film transistors (OTFTs). Here, a simple surface treatment method is applied onto an ultrathin (<15 nm) organosilicon‐based dielectric layer via the initiated chemical vapor deposition (iCVD) to make it compatible with organic semiconductors without degrading its insulating property. A molecular‐thin oxide capping layer is formed on a 15 nm thick poly(1,3,5‐trimetyl‐1,3,5‐trivinyl cyclotrisiloxane) (pV3D3) by a brief oxygen plasma treatment. The capping layer greatly enhances the thermal stability of the dielectrics, without degrading the original mechanical flexibility and insulating performance of the dielectrics. Moreover, the surface silanol functionalities formed by the plasma treatment can also be utilized for the surface modification with silane compounds. The surface‐modified dielectrics are applied to fabricate low‐voltage operating (<5 V) pentacene‐based OTFTs. The highest field‐effect mobility of the device with the surface‐treated 15 nm thick pV3D3 is 0.59 cm2 V−1 s−1, which is improved up to two times compared to the TFT with the pristine pV3D3. It is believed that the simple surface treatment method can widely extend the applicability of the highly robust, ultrathin, and flexible pV3D3 gate dielectrics to design the surface of the dielectrics to match well various kinds of organic semiconductors.