Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation
Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation
复制标题
DOI：
10.1109/isqed.2010.5450400
复制
发表时间：
2010-03
期刊：
影响因子：
--
通讯作者：
Satyanand Nalam;V. Chandra;C. Pietrzyk;R. Aitken;B. Calhoun
中科院分区：
文献类型：
--
作者：
Satyanand Nalam;V. Chandra;C. Pietrzyk;R. Aitken;B. Calhoun
本文描述了一种非对称单端6T SRAM位单元，它与传统的对称6T相比，在相同的位单元面积下同时提高了读静态噪声容限(RSNM)和写噪声容限(WNM)。这种改进是使用单个VDD实现的，而不需要使用需要多个电压的辅助技术。噪声容限的提高显著提高了SRAM的低电压稳健性，从而提高了SRAM的最小工作电压(VMIN)。使用双字线分两个阶段完成单端写入。最后，我们提出了一种使用弱参考单元来读取单端6T的差分感测方案。对于相同的位单元面积，减少的位线电容和增加的驱动电流相结合，可确保读取延迟可与传统的差分感测相媲美。
This paper describes an asymmetric single-ended 6T SRAM bitcell that improves both Read Static Noise Margin (RSNM) and Write Noise Margin (WNM) for the same bitcell area as a conventional symmetric 6T. This improvement is achieved using a single VDD, without employing assist techniques that require multiple voltages. The improvement in noise margins significantly improves the low-voltage robustness and consequently the minimum operating voltage of the SRAM (VMIN). Single-ended write is accomplished in two phases using dual word-lines. Finally, we propose a differential sensing scheme using a weak reference cell to read the single-ended 6T. A combination of reduced bitline capacitance and increased drive current ensure read delay comparable to conventional differential sensing, for the same bitcell area.