An integrated 9-channel time digitizer with 30 ps resolution

An integrated 9-channel time digitizer with 30 ps resolution
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分辨率为 30 ps 的集成 9 通道时间数字转换器

DOI:
10.1109/isscc.2002.993038
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发表时间:
2002
期刊:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
影响因子:
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通讯作者:
J. Kostamovaara
J. Kostamovaara
中科院分区:
--
文献类型:
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作者:
A. Mantyniemi;T. Rahkonen;J. Kostamovaara

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相似文献

集成式9通道时间数字化仪采用0.6 /spl mu/m CMOS工艺,具有30 ps RMS分辨率、496 /spl mu/s范围和50 mW功耗,采用三级延迟线插值和延迟生成原理,仅使用45个延迟元件将66 MHz时钟周期划分为512个bin。
An integrated 9-channel time digitizer with 30 ps RMS resolution, 496 /spl mu/s range, and 50 mW power consumption in 0.6 /spl mu/m CMOS uses a three-stage delay line interpolation and delay-generation principle that divides the 66 MHz clock period into 512 bins using only 45 delay elements.