Extended instructions for the AES cryptography and their efficient implementation
Extended instructions for the AES cryptography and their efficient implementation
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AES 密码学的扩展指令及其高效实现
DOI：
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发表时间：
2004
期刊：
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通讯作者：
Ichiro Kuroda
中科院分区：
文献类型：
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作者：
K. Nadehara;M. Ikekawa;Ichiro Kuroda
本文提出了一种在嵌入式处理器中实现高级加密标准（AES）密码加速的扩展指令及其高效实现方法。这些AES指令从AES状态的每个输入以单指令、多数据格式生成四个元素。通过使用所提出的AES指令，128位密钥AES加密的指令数可以从每个128位块的688个减少到340个。AES指令的执行单元可以用单个2Kbit表和四个小乘法器有效地实现。与传统的快速软件算法相比，该表的容量减少到1/32。AES指令使低成本网络设备的嵌入式处理器能够以最小的修改具有加密能力。
In this paper, extended instructions for the advanced encryption standard (AES) cryptography acceleration in embedded processors and efficient implementation of these instructions are presented. These AES instructions generate four elements in single-instruction, multiple-data format from each input of an AES state. The instruction count for 128-bit key AES encryption can be reduced from 688 to 340 per 128-bit block by using the proposed AES instructions. The execution unit for the AES instructions can be implemented efficiently with a single 2-Kbit table and four small multipliers. The capacity of the table has been reduced to 1/32, compared to that of a conventional fast software algorithm. The AES instructions enable embedded processors for low-cost network equipment to have cryptographic capability with minimal modification.