High Throughput Floating-Point Dividers Implemented in FPGA
High Throughput Floating-Point Dividers Implemented in FPGA
复制标题
在 FPGA 中实现的高吞吐量浮点除法器
DOI：
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
P. Malík
中科院分区：
文献类型：
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作者：
P. Malík
基于不同的快速除法算法，提出了一种新的高吞吐量浮点除法器的FPGA实现。硬件实现使用32位浮点单精度。实现包括乘法逆和除法。所提出的硬件实现被设计成具有高计算速度和吞吐量。它们面向高计算要求的应用程序，在短序列中进行多个除法计算。
New high throughput floating-point dividers implemented in FPGA based on different fast computation division algorithms are proposed. The hardware implementations uses 32-bit floating-point single precision. The implementations include both multiplicative inverse and division. The proposed hardware implementations are designed with high computation speed and throughput. They are oriented for high computation demanding applications with multiple division computations in short sequences.