Digital predistortion architecture with reduced ADC dynamic range
Digital predistortion architecture with reduced ADC dynamic range
复制标题
数字预失真架构降低了 ADC 动态范围
DOI：
10.1049/el.2015.4174
复制
发表时间：
2016
影响因子：
1.1
通讯作者：
Xin Quan
中科院分区：
文献类型：
--
作者：
Ying Liu;Xin Quan
提出了一种数字预失真（DPD）架构，减小了反馈通道的动态范围。在此架构中，部署了额外的射频 (RF) 链来消除功率放大器 (PA) 输出信号的线性分量，从而降低反馈通道的模数转换器 (ADC) 的动态范围要求。随后在数字域中，根据射频消除信号的数字副本和消除后获取的残余信号来估计原始PA输出信号，该信号用于提取DPD系数。实验结果验证了所提出架构的有效性和卓越性能，特别是在 ADC 位数减少的情况下。
A digital predistortion (DPD) architecture is proposed with the dynamic range of the feedback channel being reduced. In this architecture, an extra radio frequency (RF) chain is deployed to cancel the linear components of the power amplifier (PA) output signal to reduce the dynamic range requirement on the analogue-to-digital converter (ADC) of the feedback channel. Subsequently in digital domain, the original PA output signal is estimated from both the digital replica of the RF cancelling signal and the acquired residual signal after cancellation, which is utilised to extract the DPD coefficients. Experimental results validate the effectiveness and superior performances of the proposed architecture, particularly with the number of ADC bits being reduced.