A design of 700 MHz frequency band LTE receiver front-end with 65 nm CMOS process
A design of 700 MHz frequency band LTE receiver front-end with 65 nm CMOS process
复制标题
采用65 nm CMOS工艺的700 MHz频段LTE接收前端设计
DOI：
10.1109/apmc.2009.5384241
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
Yoosam Na
中科院分区：
文献类型：
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作者：
Hyeonseok Hwang;Hyunhwan Yoo;Munsun Kim;Yoosam Na
提出了一种700 MHz频段长期演进(LTE)接收机前端的设计方案。线性度和噪声系数是3GPP标准中描述的测试用例所规定的LTE接收机的关键参数。通过对LTE规范的分析，设计了LNA和混频电路。根据外部SAW的使用情况，实现了两种类型的LNA。两种低噪声放大器的增益分别为18.75dBm、1.5dBnF，−分别为0.1dBm、IIP3。为了提高IIP2的性能，在有源型的基础上，采用电流注入的方法设计了混频器。其增益为15.4dBm，噪声为6.4dBm，IIP3为0.5dBm。所有电路均采用65 nm工艺设计，电源电压为1.8V。整个接收链的测试结果显示，在-QAM调制下，−为34.8dBEVM，系统噪声为3.2dBEVM。
A receiver front-end of LTE (Long Term Evolution) at 700 MHz frequency band is proposed. Linearity and noise figure is key parameter of LTE receiver specified by test cases described in 3GPP standard. From the analysis of the specification of LTE, LNA and mixer circuits are comprised. Two types of LNA are implemented depending on the external SAW usage. Both LNAs show 18.75 dB gain, 1.5 dB NF and −0.1 dBm IIP3. The mixer is designed based on active type with current injection method to increase IIP2 performance. It shows 15.4 dB gain, 6.4 dB NF and 0.5 dBm IIP3. All the circuits are designed in 65 nm CMOS process with 1.8 V supply. The measurements of whole receiver chain show −34.8 dB EVM at 64-QAM modulation and 3.2 dB system NF.