Electronic Band Offset Determination of Oxides Grown by Atomic Layer Deposition on Silicon
Electronic Band Offset Determination of Oxides Grown by Atomic Layer Deposition on Silicon
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DOI：
10.1109/jphotov.2023.3291048
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发表时间：
2023-09
影响因子：
3
通讯作者：
E. Khorani;Christoph Messmer;S. Pain;T. Niewelt;B. F. M. Healy;A. Wratten;M. Walker;N. Grant;J. Murphy
中科院分区：
文献类型：
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作者：
E. Khorani;Christoph Messmer;S. Pain;T. Niewelt;B. F. M. Healy;A. Wratten;M. Walker;N. Grant;J. Murphy
在高效单结硅太阳能电池中，最小化金属/硅界面的电损耗需要使用载流子选择性钝化触点。绝缘体/硅界面上的电子势垒高度是计算这些界面上载流子量子隧穿概率所必需的。因此，这些参数的精确知识对于接触方案的发展至关重要。利用光电发射方法，实验测定了原子层沉积（ALD）在硅上生长的Al2O3、HfO2和SiO2层的电子能带偏移量。对于Al2O3/Si，我们确定了价带偏移（ΔEV）和导带偏移（ΔEC）分别为3.29±0.07 eV和2.24±0.13 eV。对于HfO2/Si， ΔEV和ΔEC分别为2.67±0.07 eV和1.81±0.21 eV，对于SiO2/Si， ΔEV和ΔEC分别为4.87±0.07 eV和2.61±0.12 eV。利用计算机辅助设计模拟技术，我们结合我们的实验结果来估计在不同介电层厚度下将获得的接触电阻率。我们发现，为了达到100 mΩ·cm2的接触电阻率基准，对于p型多晶硅基的空穴选择接触，假设从文献中获得的空穴隧道质量，Al2O3层的厚度应不大于1.65 nm。相应地，对于HfO2和SiO2，确定了1.4 nm的上限作为厚度阈值，以便在高性能硅光伏电池中利用这些ald生长层的触点。
Minimizing electrical losses at metal/silicon interfaces in high-efficiency single-junction silicon solar cells requires the use of carrier-selective passivating contacts. The electronic barrier heights at the insulator/silicon interface are necessary for calculating the probability of quantum tunneling of charge carriers at these interfaces. Thus, precise knowledge of these parameters is crucial for the development of contact schemes. Using a photoemission-based method, we experimentally determine the electronic band offsets of Al2O3, HfO2 and SiO2 layers grown by atomic layer deposition (ALD) on silicon. For Al2O3/Si, we determine a valence band offset (ΔEV) and conduction band offset (ΔEC) of 3.29 ± 0.07 eV and 2.24 ± 0.13 eV, respectively. For HfO2/Si, ΔEV and ΔEC are determined as 2.67 ± 0.07 eV and 1.81 ± 0.21 eV, while for SiO2/Si, ΔEV and ΔEC are 4.87 ± 0.07 eV and 2.61 ± 0.12 eV, respectively. Using technology computer-aided design simulations, we incorporate our experimental results to estimate the contact resistivity that would be attained at various dielectric layer thicknesses. We find that for achieving the 100 mΩ·cm2 contact resistivity benchmark, Al2O3 layers should be no thicker than 1.65 nm for a p-type polysilicon-based hole-selective contact, assuming hole tunneling masses taken from the literature. Correspondingly, for HfO2 and SiO2, an upper limit of 1.4 nm is determined as the thickness threshold in order to utilize these ALD-grown layers for contacts in high-performance silicon photovoltaics.