Constant coefficient multiplication in FPGA structures
Constant coefficient multiplication in FPGA structures
复制标题
FPGA 结构中的常数系数乘法
DOI：
10.1109/eurmic.2000.874640
复制
发表时间：
2000
期刊：
影响因子：
--
通讯作者：
E. Jamro
中科院分区：
文献类型：
--
作者：
K. Wiatr;E. Jamro
研究了在FPGA结构中实现位平行恒定乘积的不同体系结构。首先，解决了采用概念符号数字（CSD）和子结构共享方法的无乘数乘法（MM）体系结构，并提出了一种从两个组合到CSD表示的转换的新颖算法。在本文的第二部分中，研究了基于查找的乘法（LM）。相应地，考虑了不同的内存模块的使用并找到内存和加法器的最佳组合。 LM体系结构还考虑了每个内存单元格的地址宽度的减少以及内存子结构共享的可能性。最后，提出了Xilinx XC4000和Virtex家族的实施结果。结果，MM通常超过LM体系结构。但是，这两个体系结构之间的实际选择是系数和输入参数依赖性。
Investigates different architectures implementing bit-parallel constant-coefficient multiplication in FPGA structures. First, multiplierless multiplication (MM) architectures employing canonic sign digit (CSD) and sub-structure sharing methods are addressed, and a novel algorithm for the conversion from two's-complement to CSD representation is presented. In the second part of this paper, lookup table-based multiplication (LM) is investigated. Correspondingly, the usage of different memory modules and finding the optimal combination of the memory and adders are considered. The LM architecture also considers reduction of the address width for each memory cell and the possibility of memory sub-structure sharing. Finally, implementation results for the Xilinx XC4000 and Virtex families are presented. As a result, MM generally surpasses the LM architecture. However, the actual choice between these two architectures is coefficient- and input parameter-dependent.