A Spline-High Dimensional Model Representation for SRAM Yield Estimation in High Sigma and High Dimensional Scenarios
A Spline-High Dimensional Model Representation for SRAM Yield Estimation in High Sigma and High Dimensional Scenarios
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DOI：
10.1109/access.2021.3067510
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发表时间：
2021
期刊：
影响因子：
3.9
通讯作者：
Liang-Teck Pang;Shan Shen;Mengyun Yao
中科院分区：
文献类型：
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作者：
Liang-Teck Pang;Shan Shen;Mengyun Yao
传统的静态随机存取存储器(SRAM)通过蒙特卡罗分析来估计成品率是一个非常耗时的过程，因为它需要运行数百万个昂贵的晶体管级仿真来获得指定精度的成品率结果，特别是对于大规模电路。在本文中，我们通过将我们新的性能元模型集成到最新的重要性抽样方法中，开发了一个有效的收益率分析框架。性能元模型被称为Spline高维模型表示(SP-HDMR)，用于替代昂贵的晶体管级模拟用于成品率估计。所提出的SP-HDMR模型提供了高计算效率的公式扩展。它以样条函数为核，描述了工艺参数与SRAM读访问延迟之间的各种关系。提出了一种基于稀疏性分析的自适应采样方法来支持SP-HDMR建模。在40 nm SRAM电路上的实验验证了基于SP-HDMR模型的成品率分析框架的准确性和效率，相对误差在9%以内，成品率分析框架比其他现有方法有1.3倍的$\sim 5\text{X}$的加速比。
Traditional Static Random-Access Memory (SRAM) yield estimation through Monte Carlo analysis is an extremely time-consuming process since it runs millions of expensive transistor-level simulations to get the yield results with the specified precision, especially for the large-scale circuits. In this paper, we develop an efficient yield analysis framework by integrating our novel performance metamodel into a state-of-art importance sampling method. The performance meta-model, named Spline-High Dimensional Model Representation (SP-HDMR), is used to substitute the expensive transistor-level simulations in yield estimation. The proposed SP-HDMR model provides a high computationally efficient formula expansion. It uses spline functions as the kernels to describe the various relations between the process parameters and SRAM read access delay. And an adaptive sampling method with sparsity analysis is developed to support SP-HDMR modeling. The experiments on the 40nm SRAM circuits validate the accuracy and the efficiency of the proposed yield analysis framework based on our SP-HDMR model with 1.3X $\sim 5\text{X}$ speedup over the other state-of-art methods within 9% relative error.