Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging
Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging
复制标题
用于先进芯片级封装的硅基晶圆互连制造
DOI：
10.1016/j.sna.2007.02.030
复制
发表时间：
2008
影响因子：
4.6
通讯作者：
M. Juntunen
中科院分区：
文献类型：
--
作者：
F. Ji;S. Leppävuori;I. Luusua;K. Henttinen;S. Eränen;I. Hietanen;M. Juntunen
提出了一种通过刻蚀、填充和研磨实现穿晶互连的方法。基于这种方法，先进的芯片级封装（CSP）。与倒装芯片技术相比，基于硅的传感器或致动器，特别是大规模检测器阵列，可以组装成感测表面向上的系统，然后可以通过使用TWI从芯片的背面提取电信号，而不牺牲正面感测表面。此外，它还使3D芯片堆叠成为可能。一般来说，从制造的晶片测量到小于1.5pF的电容和240Ω的电阻。为了更好地将TWI集成到不同的传感器系统中，基于金属氧化物半导体（MOS）模型讨论了改变TWI电容的能力。从漏电流模拟结果，在TWIs的处理过程中可能存在的缺陷，并通过引入不同的故障机制的TWIs的绝缘检测。因此，TWI的制造及其相关的CSP工艺已经证明，这是一个有前途的技术，为一系列的传感器应用。
This paper presents a fabrication method to achieve through-wafer interconnects (TWIs) by etching, filling and grinding in sequence. Based on this method, advanced chip scale packaging (CSP) is performed. Compared to flip-chip technology, silicon based sensors or actuators, especially large scale detector arrays, can be assembled into a system with the sensing surface upwards, and electrical signals can then be extracted from the back side of the chip without sacrificing the front sensing surface by using TWIs. In addition, it also makes 3-D chip stacking possible. Generally speaking, less than 1.5pF capacitance and 240Ω resistance are measured from the fabricated wafer. In order to better integrate the TWIs into different sensor systems, the ability to vary the capacitance of the TWIs is discussed based on a metal-oxide-semiconductor (MOS) model. From leakage current simulation results, possible defects during the processing of TWIs are addressed and detected by introducing different failure mechanisms of the insulation of the TWIs. As a result, the fabrication of TWIs and their related CSP procedure have proved that it is a promising technology for a range of sensor applications.