Side-wall spacer passivated sub-μm Josephson junction fabrication process
Side-wall spacer passivated sub-μm Josephson junction fabrication process
复制标题
侧壁间隔钝化亚μm约瑟夫森结制造工艺
DOI:
10.1088/1361-6668/aa9411
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发表时间:
2017
影响因子:
3.6
通讯作者:
J. Hassel
中科院分区:
文献类型:
--
作者:
L. Grönberg;M. Kiviranta;V. Vesterinen;J. Lehtinen;S. Simbierowicz;J. Luomahaara;M. Prunnila;J. Hassel
We present a structure and a fabrication method for superconducting tunnel junctions down to the dimensions of 200 nm using i-line UV lithography. The key element is a sidewall-passivating spacer structure (SWAPS) which is shaped for smooth crossline contacting and low parasitic capacitance. The SWAPS structure enables formation of junctions with dimensions at or below the lithography-limited linewidth. An additional benefit is avoiding the excessive use of amorphous dielectric materials which is favorable in sub-Kelvin microwave applications often plagued by nonlinear and lossy dielectrics. We apply the structure to niobium trilayer junctions, and provide characterization results yielding evidence on wafer-scale scalability, and critical current density tuning in the range of 0.1–3.0 kA cm−2. We discuss the applicability of the junction process in the context of different applications, such as SQUID magnetometers and Josephson parametric amplifiers.