Estimation of power distribution in VLSI interconnects
Estimation of power distribution in VLSI interconnects
复制标题
VLSI 互连中的功率分布估计
DOI：
10.1109/lpe.2001.945434
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
T. Sakurai
中科院分区：
文献类型：
--
作者：
Youngsoo Shin;T. Sakurai
随着工艺技术规模的不断缩小，对超大规模集成电路互连效应的分析和仿真变得越来越重要。虽然大多数分析都集中在互连的时序方面，但功耗也很重要。本文利用降阶模型研究了互连线的功率分布估计问题。推导出了功率消耗与传递函数的极点和残差之间的关系，并建立了相应的驱动器模型，从而有效地计算出功率消耗。所提出的方法RC网络的应用程序演示使用原型工具。
The analysis and simulation of effects induced by VLSI interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution estimation of interconnects is studied using a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. Application of the proposed method to RC networks is demonstrated using a prototype tool.