Optimization of standard cell based detailed placement for 16 nm FinFET process
Optimization of standard cell based detailed placement for 16 nm FinFET process
复制标题
基于标准单元的 16 nm FinFET 工艺详细布局优化
DOI：
10.7873/date2014.370
复制
发表时间：
2014
期刊：
影响因子：
--
通讯作者：
Martin D. F. Wong
中科院分区：
文献类型：
--
作者：
Yuelin Du;Martin D. F. Wong
FinFET 晶体管在高性能和低功耗应用中比传统平面 MOSFET 晶体管具有巨大优势。主要代工厂正在采用 Fin-FET 技术来制造 16 纳米及以上技术节点的 CMOS 半导体器件。边缘器件退化是 FinFET 工艺面临的主要挑战之一。为了避免这种退化，器件边缘需要虚拟栅极，并且虚拟栅极必须连接到电源轨，以免引入未连接的寄生晶体管。这要求每个虚拟栅极在标准单元放置之后必须邻接至少一个源节点。如果两个相邻单元边界处的漏极节点彼此相邻，则必须在其间插入额外的源极节点以用于虚拟栅极电源连接，这会花费更多的放置面积。通常在详细布局时会有一定的灵活性，可以水平翻转单元格或切换相邻单元格的位置，这对全局布局目标（例如时序条件和网络拥塞）影响很小。本文提出了基于标准单元的设计的详细布局优化策略。通过翻转标准单元行中的单元子集并切换相邻单元对，可以最佳地最小化相邻单元边界之间的漏极邻接的数量，这节省了额外的源节点插入并减少了标准单元行的长度。此外，所提出的图模型可以很容易地修改以考虑更复杂的设计规则。实验结果表明，0.1秒内完成了10万个单元的优化，验证了所提算法的效率。
FinFET transistors have great advantages over traditional planar MOSFET transistors in high performance and low power applications. Major foundries are adopting the Fin-FET technology for CMOS semiconductor device fabrication in the 16 nm technology node and beyond. Edge device degradation is among the major challenges for the FinFET process. To avoid such degradation, dummy gates are needed on device edges, and the dummy gates have to be tied to power rails in order not to introduce unconnected parasitic transistors. This requires that each dummy gate must abut at least one source node after standard cell placement. If the drain nodes at two adjacent cell boundaries abut each other, additional source nodes must be inserted in between for dummy gate power tying, which costs more placement area. Usually there is some flexibility during detailed placement to horizontally flip the cells or switch the positions of adjacent cells, which has little impact on the global placement objectives, such as timing conditions and net congestion. This paper proposes a detailed placement optimization strategy for the standard cell based designs. By flipping a subset of cells in a standard cell row and switching pairs of adjacent cells, the number of drain to drain abutments between adjacent cell boundaries can be optimally minimized, which saves additional source node insertion and reduces the length of the standard cell row. In addition, the proposed graph model can be easily modified to consider more complicated design rules. The experimental results show that the optimization of 100k cells is completed within 0.1 second, verifying the efficiency of the proposed algorithm.