Impact of HKMG and FDSOI FeFET drain current variation in processing-in-memory architectures
Impact of HKMG and FDSOI FeFET drain current variation in processing-in-memory architectures
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DOI：
10.1557/s43578-021-00393-1
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发表时间：
2021-09
影响因子：
2.7
通讯作者：
Nathan Eli Miller;Zheng Wang;Saurabh Dash;A. Khan;S. Mukhopadhyay
中科院分区：
文献类型：
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作者：
Nathan Eli Miller;Zheng Wang;Saurabh Dash;A. Khan;S. Mukhopadhyay
在本研究中，我们分析了漏极电流的影响 (IDS\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$ I_{{{\text{DS}}}} $$\end{document}) 内存处理 (PIM) 深度神经网络 (DNN) 加速器上 28 nm 高 K 金属栅极和 22 nm 全耗尽绝缘体上硅铁电 FET 器件的变化。当在不同的读取频率和不同的偏置和编程条件下在多个设备上执行重复读取操作时，IDS\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} 中出现非正态变化\setlength{\oddsidemargin}{-69pt} \begin{document}$$ I_{{{\text{DS}}}} $$\end{document} 被观察到。器件电路协同分析用于模拟图像分类时受到噪声影响的 PIM 性能。使用 LeNet-5 在 Fashion-MNIST 分类精度中观察到边际退化，在使用 MobileNetV2 的 CIFAR-10 分类精度中观察到更显着的退化。研究表明，变化感知训练可以完全恢复 LeNet-5 准确性的微小下降，但对于 MobileNetV2 等大型工作负载来说变得困难。我们证明了 IDS\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$ I_{{{\text{DS}}}} $$\end{document} 单个 FeFET 在多个读取周期中的变化并不妨碍设计小工作负载的 DNN 加速器，但需要先进的设计技术来减少较大工作负载的错误。
In this study, we analyze the impact of drain current (IDS\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$ I_{{{\text{DS}}}} $$\end{document}) variation in 28 nm high-K metal-gate and 22 nm fully-depleted silicon-on-insulator Ferroelectric FET devices on processing-in-memory (PIM) deep neural network (DNN) accelerators. When performing repeated read operations on several devices at various read frequencies and under various biasing and programming conditions, non-Normal variation in IDS\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$ I_{{{\text{DS}}}} $$\end{document} is observed. Device-circuit co-analysis is used to emulate PIM performance subject to noise when classifying images. Marginal degradation is observed in Fashion-MNIST classification accuracy using LeNet-5, and more significant degradation is observed in CIFAR-10 classification accuracy using MobileNetV2. Variation-aware training is shown to fully recover minor drops in LeNet-5 accuracy but becomes difficult for large workloads like MobileNetV2. We demonstrate that IDS\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$ I_{{{\text{DS}}}} $$\end{document} variation in individual FeFETs over many read cycles is not prohibitive to designing DNN accelerators with small workloads, but advanced design techniques are required to mitigate error for larger workloads.