A new code-disjoint sum-bit duplicated carry look-ahead adder for parity codes
A new code-disjoint sum-bit duplicated carry look-ahead adder for parity codes
复制标题
用于奇偶校验码的新的码不相交和位重复进位先行加法器
DOI：
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
M. Gössel
中科院分区：
文献类型：
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作者：
V. Ocheretnij;E. Sogomonyan;M. Gössel
提出了一种新的码不相交自校验超前进位加法器。为了减少所需的面积和功耗，仅复制加法器单元的和位。这是可能的，因为通过使用加法器单元的内部节点来确定输入奇偶校验。加法器是由EUROCHIP项目的SYNOPSIS CAD工具与标准库建模。关于复制和比较，与仅增加12%的最大延迟相比，所需面积和功耗可以分别减少高达38%和高达29%。
A new code-disjoint self-checking carry look-ahead adder is proposed. To reduce the necessary area and the power dissipation only the sum bits of the adder cells are duplicated. This is possible since the input parity is determined by use of internal nodes of the adder cells. The adder is modeled by a SYNOPSIS CAD tool from the EUROCHIP-Project with a standard library. With respect to duplication and comparison the necessary area and the power dissipation can be reduced up to 38 % and up to 29 % respectively compared to an increase of the maximal delay of only 12 %.