RETROSPECTIVE: Wattch: A Framework for Architectural-level Power Analysis and Optimizations
RETROSPECTIVE: Wattch: A Framework for Architectural-level Power Analysis and Optimizations
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发表时间：
2023
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通讯作者：
D. Brooks;V. Tiwari;Intel Margaret Martonosi
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作者：
D. Brooks;V. Tiwari;Intel Margaret Martonosi
大约1990年代中期，在微处理器路线图上有麻烦的迹象。阈值泄漏和脱钩电容器正在进入建筑师的词典，但他们没有简单的方法将这些低级微观现象与高级宏观建筑的决定联系起来。自1990年代初以来，对CPU架构研究社区引入了急需的定量方法。建筑师，但主要是在电池驱动器移动或嵌入式系统的低功率设计中，这并不是CPU建筑师认为他们需要作为主要限制的问题，因为热耗散和功率交付成本仍然可以管理缩放尚未达到“泄漏屏障”，以防止电压和门氧化物厚度降低（光线有限速度！）建筑社区。其余的文章并未明确说明即将来临的现实，即权力将成为CPU的主要限制事实上，关于电力驱动的微观结构的第一个讲习班与巴塞罗那的ISCA'98结合（在一个小房间里，有一个小但高度参与的观众）。优化绩效折衷方案，但一个关键的障碍是如何在Power-Inave Architecture中使用“代理指标”来量化不同的想法。 Martonosi考虑了狭窄的操作，并提供了可以使用这种优化的频率[3]，但是缺少的是整体架构级功率模型，可以用来运行模拟，就像使用指令模拟器一样用于量化建筑建议的绩效益处。
Circa mid-1990s there are signs of trouble brewing on the microprocessor roadmap horizon. Traditional Dennard scaling is running out of steam. CPU architects can no longer count on process technologists and circuit designers to give them power reduction for free. Terms like switched capacitance, sub-threshold leakage and decoupling capacitors were entering the lexicon of architects. But they have no easy way to relate these low-level micro phenomena to high-level macro architectural decisions. This was the environment at the time when Wattch appeared on the scene, introducing a much needed quantitative approach to power to the CPU architecture research community. Power considerations were already prominent for researchers in circuits and design automation topic areas since the early 1990’s. By the late 1990’s, they were beginning to also be on the minds of computer architects but mostly in the context of low power designs for battery driven mobile or embedded systems. This was not yet a problem that highperformance CPU architects felt they needed to tackle as a primary constraint since thermal dissipation and power delivery costs were still manageable. Process technology scaling had not yet hit the “leakage barrier” that was soon going to prevent both voltage and gate oxide thickness reductions. Cross-chip communication (the finite speed of light!) and the limits of instruction-level parallelism were the hot topics in the architecture community. The special issue of IEEE Computer in September 1997 [1] that resulted as a followup to a vigorous debate at ISCA’96, was focused on options for Billion Transistor CPUs. Other than a brief mention of power in the introductory editorial, the rest of the articles did not explicitly address the impending reality that power was going to be the primary limiter for performance for general purpose CPUs. But this was changing [2] and the awareness of power issues among CPU architects was ramping up rapidly. In fact the first Workshop on Power-Driven Microarchitecture was held in conjunction with ISCA’98 in Barcelona (in a small room with a small but highly engaged audience). We were excited about the opportunities to demonstrate how architectural techniques could mitigate power dissipation challenges and optimize power-performance tradeoffs, but a key hurdle was how to offer quantitative results on the promise and potential of different ideas. Early work in power-aware architecture would use “proxy metrics” to quantify benefits. For example, an earlier paper from Brooks and Martonosi considered narrow-bitwidth operations and offered results on how frequently such optimizations could be applied [3]. What was missing, however, was a holistic architecture-level power model that could be used to run simulations just as instructionlevel simulators were commonly used for quantifying the performance benefits of architectural proposals.