Area-Efficient Error Protection for Caches
Area-Efficient Error Protection for Caches
复制标题
缓存的区域高效错误保护
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
Soontae Kim
中科院分区：
文献类型：
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作者：
Soontae Kim
由于对各种错误的担忧越来越大，当前的处理器采用了错误保护机制。特别是，由于错误校正代码，保护L2/L3缓存的面积高达12.5％。考虑到当前处理器的大型L2/L3缓存，头顶的区域很高。本文提出了针对L2/L3缓存的面积效率保护方案。首先，它选择性地将ECC（错误校正代码）应用于肮脏的缓存线，而其他干净的高速缓存线则使用简单的奇偶校验检查代码进行保护。其次，通过利用缓存线的世代行为来定期清洁肮脏的缓存线。实验结果表明，清洁技术有效地减少了每个周期的肮脏缓存线的数量。减少的肮脏高速缓存线的ECC可以保持在较小的存储空间中。我们提出的方案显示，对于在典型的四级超尺度处理器上运行的Spec2000基准，可以将1MB L2缓存的面积减少59％，以减少59％。
Due to increasing concern about various errors, current processors adopt error protection mechanisms. Especially, protecting L2/L3 caches incur as much as 12.5% area overhead due to error correcting codes. Considering large L2/L3 caches of current processors, the area overhead is very high. This paper proposes an area-efficient error protection scheme for L2/L3 caches. First, it selectively applies ECC (error correcting code) to only dirty cache lines and other clean cache lines are protected using simple parity check codes. Second, the dirty cache lines are periodically cleaned by exploiting the generational behavior of cache lines. Experimental results show that the cleaning technique effectively reduces the number of dirty cache lines per cycle. The ECCs of this reduced number of dirty cache lines can be maintained in a small storage. Our proposed scheme is shown to reduce the area overhead of a 1MB L2 cache for error protection by 59% for SPEC2000 benchmarks running on a typical four-issue superscalar processor