A generalized hardware architecture for real-time spiking neural networks
A generalized hardware architecture for real-time spiking neural networks
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DOI：
10.1007/s00521-023-08650-6
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发表时间：
2023-05-24
影响因子：
6
通讯作者：
Alimohammad，Amir
中科院分区：
文献类型：
--
作者：
Valencia，Daniel;Alimohammad，Amir
本文提出了一种用于脑植入式脉冲神经网络（SNN）的面积和功耗有效的硬件架构。所提出的广义硬件架构是可参数化和可重构的，使得最大支持的神经元数量，神经元之间的互连结构，以及时间步长的分辨率可以很容易地调整，以实现各种SNN拓扑结构。所设计的SNN硬件架构能够以不同程度的并行性实时仿真具有数万个神经元的中等大小的SNN，同时对于在单个现场可编程门阵列（FPGA）上实现的类似大小的SNN，将资源利用率降低了34%。我们使用MNIST数字识别基准对模型进行了评估，结果表明该网络可以准确地对手写数字进行分类，准确率为89.8%。与其他最近实现的基于FPGA的SNN仿真器相比，所设计和实现的单FPGA系统能够仿真中等大小的SNN，而不是使用FPGA或CPU的集群。一个中等大小的SNN的专用集成电路（ASIC）实现估计占用3.6 mm2的硅面积。布局后的综合和仿真结果表明，ASIC将消耗3.6 mW的功率从1.16 V电源，同时在34.7 MHz的标准32纳米CMOS工艺。
This article presents an area- and power-efficient hardware architecture for the brain-implantable spiking neural networks (SNNs). The proposed generalized hardware architecture is parameterizable and reconfigurable such that the maximum supported number of neurons, the interconnection structure among neurons, and the resolution of the time step can be readily adjusted for realizing various SNN topologies. The designed SNN hardware architecture is capable of emulating moderately-sized SNNs with tens of thousands of neurons in real-time with varying degrees of parallelism, while reducing the resource utilization by 34% for similarly sized SNNs implemented on a single field-programmable gate array (FPGA). We evaluate the model using the MNIST digit recognition benchmark and show that the network can accurately classify handwritten digits with 89.8% accuracy. Compared to the other recently implemented SNN emulators based on FPGAs, the designed and implemented single-FPGA system is able to emulate moderately-sized SNNs instead of using a cluster of FPGAs or CPUs. The application-specific integrated circuit (ASIC) implementation of a moderately-sized SNN is estimated to occupy 3.6 mm2of silicon area. Post-layout synthesis and simulation results show that the ASIC will dissipate 3.6 mW of power from a 1.16 V supply while operating at 34.7 MHz in a standard 32-nm CMOS process.