264 Channel TDC Platform applying 65 channel high precision (7.2 psRMS) FPGA based TDCs
264 Channel TDC Platform applying 65 channel high precision (7.2 psRMS) FPGA based TDCs
复制标题
264 通道 TDC 平台应用基于 65 通道高精度 (7.2 psRMS) FPGA 的 TDC
DOI：
--
复制
发表时间：
2013
期刊：
影响因子：
--
通讯作者：
M. Traxler
中科院分区：
文献类型：
--
作者：
C. Ugur;G. Korcyl;J. Michel;Manuel Penschuk;M. Traxler
本文介绍了一种用单现场可编程门阵列(FPGA)实现的65通道高精度时间-数字转换器。贸发局采用插值法测量时间。利用波联发射器方法提高了TDC的精度。为了克服最小脉冲宽度的限制，实现了半异步脉冲展宽器，该展宽器已被验证可以测量500ps的脉冲宽度。TDC在单个通道上的典型精度为7.2 ps rms(最差通道为14 ps rms)。此外，本文还介绍了264通道TDC平台--TDC读出板(TRB3)。
In this paper the implementation of a 65 channel high precision Time-to-Digital Converter in a single Field Programmable Gate Array (FPGA) is presented. The TDC applies the interpolation method for time measurements. The precision of the TDC is increased with the Wave Union Launcher method. In order to overcome the minimum pulse width limitation a semi-asynchronous pulse stretcher is implemented which has been verified to allow a measurement of a pulse width <; 500 ps. The TDC has a typical precision of 7.2 ps RMS (14 ps RMS on the worst channel) on a single channel. Additionally, the 264 Channel TDC Platform, TDC Readout Board (TRB3), is presented in the paper applying the described TDC.