A Network-on-Chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs
A Network-on-Chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs
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用于嵌入式多处理器 SoC 以通信为中心的调试的片上网络监控基础设施
DOI：
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发表时间：
2009
期刊：
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通讯作者：
K. Goossens
中科院分区：
文献类型：
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作者：
B. Vermeulen;K. Goossens
由硬件和嵌入式软件组成的新的片上系统（SOC）中的问题通常只在芯片的硅原型被放置在其预期的目标环境中并执行应用程序时才会出现。传统上，嵌入式系统的调试是困难和耗时的，因为内在的系统在目标环境中缺乏可观测性和可控制性。可调试设计（DfD）是在芯片设计中添加调试支持的行为，因为并非每个SOC在第一次都是正确的。DfD为调试工程师提供了增强的嵌入式系统内部操作的可观察性和可控制性。在本文中，我们提出了一个多处理器的SOC与片上网络（NOC）的监测基础设施，并解释其性能分析和调试的应用。我们描述了我们的监视器如何帮助嵌入式处理器的交互的性能分析和调试。我们提出了一个通用的总线和路由器监视器的模板，并显示他们是如何在我们的NOC设计流程的设计时实例化。最后，我们详细介绍了它们的硬件成本。
Problems in a new System on Chip (SOC) consisting of hardware and embedded software often only show up when a silicon prototype of the chip is placed in its intended target environment and the application is executed. Traditionally, the debugging of embedded systems is difficult and time consuming because of the intrinsic lack of internal system observability and controlability in the target environment. Design for Debug (DfD) is the act of adding debug support to the design of a chip, in the realization that not every SOC is correct first time. DfD provides debug engineers with increased observability and controlability of the internal operation of an embedded system. In this paper, we present a monitoring infrastructure for multi-processor SOCs with a Network on Chip (NOC), and explain its application to performance analysis and debug. We describe how our monitors aid in the performance analysis and debug of the interactions of the embedded processors. We present a generic template for bus and router monitors, and show how they are instantiated at design time in our NOC design flow. We conclude this paper with details of their hardware cost.