A Vertically Integrated Pixel Readout Device for the Vertex Detector at the International Linear Collider
A Vertically Integrated Pixel Readout Device for the Vertex Detector at the International Linear Collider
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DOI：
10.1109/tns.2010.2042301
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发表时间：
2010-04
影响因子：
1.8
通讯作者：
G. Deptuch;D. Christian;J. Hoff;R. Lipton;A. Shenai;M. Trimpl;R. Yarema;T. Zimmerman
中科院分区：
文献类型：
--
作者：
G. Deptuch;D. Christian;J. Hoff;R. Lipton;A. Shenai;M. Trimpl;R. Yarema;T. Zimmerman
在未来的高能物理（HEP）实验中，跟踪和顶点涉及到由数十亿个通道组成的探测器的构建。读出电子设备必须以可达到的最高精度记录每次测量的位置和时间。本文回顾了HEP的第一个3D读出芯片的原型，设计的顶点探测器在国际直线对撞机。该原型具有20 × 20 <$m2像素，布局在64 × 64元素的阵列中，并在麻省理工学院林肯实验室采用3层0.18 <$m全耗尽SOI CMOS工艺制造。测试表明结构的功能运行正确。芯片执行零抑制读出。
Tracking and vertexing in future High-Energy Physics (HEP) experiments involves construction of detectors composed of up to a few billions of channels. Readout electronics must record the position and time of each measurement with the highest achievable precision. This paper reviews a prototype of the first 3D readout chip for HEP, designed for a vertex detector at the International Linear Collider. The prototype features 20 × 20 ¿m2 pixels, laid out in an array of 64 × 64 elements and was fabricated in a 3-tier 0.18 ¿m Fully Depleted SOI CMOS process at MIT-Lincoln Laboratory. The tests showed correct functional operation of the structure. The chip performs a zero-suppressed readout.