A high-level DRAM timing, power and area exploration tool
A high-level DRAM timing, power and area exploration tool
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高级 DRAM 时序、功率和区域探索工具
DOI：
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发表时间：
2015
期刊：
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通讯作者：
Andreas Hansson
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文献类型：
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作者：
Omar Naji;C. Weis;Matthias Jung;N. Wehn;Andreas Hansson
在从移动设备到服务器的系统中，DRAM对性能产生了很大的影响，并贡献了总消费能力的重要组成部分。系统的性能和功能取决于DRAM芯片的架构，内存控制器的设计以及内存控制器接收的访问模式。因此，评估DRAM设计决策的影响需要一种整体方法，其中包括DRAM银行的适当模型，现实的控制器和DRAM功率模型以及需要完整的系统模拟器的代表工作负载，并运行完整的软件堆栈。在本文中，我们介绍了DRAMSPEC，这是一种开源的高级DRAM银行建模工具。作为主要贡献，我们将DRAM建模抽象级别从详细的电路级别移动到DRAM库，并且通过完整系统模拟器的集成，我们允许系统或处理器设计人员（非DRAM专家）调整未来的DRAM架构，以实现其目标应用和使用案例。我们通过探索DRAM行缓冲区大小的影响以及银行对服务器应用程序的性能和功率的影响（Memcached）来证明DRAMSPEC的优点。与标准Comodity DDR3设备相比，我们的新DRAM设计可提供16％的DRAM性能提高和13％的DRAM节能。此外，我们演示了我们的工具如何帮助评估没有可用数据表的新型DRAM体系结构。
In systems ranging from mobile devices to servers, DRAM has a big impact on performance and contributes a significant part of the total consumed power. The performance and power of the system depends on the architecture of the DRAM chip, the design of the memory controller and the access patterns received by the memory controller. Evaluating the impact of DRAM design decisions therefore requires a holistic approach that includes an appropriate model of the DRAM bank, a realistic controller and DRAM power model, and a representative workload which requires a full system simulator, running a complete software stack. In this paper, we introduce DRAMSpec, an open source high-level DRAM bank modeling tool. As major contribution, we move the DRAM modeling abstraction level from detailed circuit level to the DRAM bank and by the integration in full system simulators we allow system or processor designers (non-DRAM experts) to tune future DRAM architectures for their target applications and use cases. We demonstrate the merits of DRAMSpec by exploring the influence of DRAM row buffer size and the number of banks on performance and power of a server application (memcached). Our new DRAM design offers a 16% DRAM performance improvement and 13% DRAM energy saving compared to standard comodity DDR3 devices. Additionally, we demonstrate how our tool is able to aid in evaluating novel DRAM architectures for which no datasheets are available.