A partitioning and storage based built-in test pattern generation method for scan circuits
A partitioning and storage based built-in test pattern generation method for scan circuits
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一种基于分区和存储的扫描电路内置测试模式生成方法
DOI：
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发表时间：
2002
期刊：
影响因子：
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通讯作者：
S. Reddy
中科院分区：
文献类型：
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作者：
I. Pomeranz;S. Reddy
本文提出了一种扫描电路的内建测试图形生成方法。该方法基于测试集的划分和存储。在这种方法下，一个预先计算的测试集被划分成几个集合，包含不同的主要输入或状态变量的值。片上测试集是通过实现笛卡尔积的各种集合。为了减少存储要求和测试应用时间，在将集合存储在片上之前尽可能地减少集合。
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of different primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time.