A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy
A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy
复制标题
使用混合模式自适应环路增益策略的 Bang-Bang 时钟和数据恢复
DOI：
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发表时间：
2013
影响因子：
5.4
通讯作者：
J. Silva
中科院分区：
文献类型：
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作者：
H. Jeon;R. Kulkarni;Yung;Jusung Kim;J. Silva
提出了一种具有自适应环路增益策略的Bang-Bang时钟和数据恢复（CDR）。在抖动频谱信息有限的情况下，该策略提高了话单抖动性能。利用Bang-Bang鉴相器固有的硬非线性特性，基于后验抖动谱估计自适应调整CDR环路增益。最大限度地发挥模拟和数字实现的优势，所提出的混合模式技术实现了PVT不敏感和功率高效的环路增益适应，即使在有限的ft技术中也适用于高速应用。改进的CML d锁存器提高了CDR输入灵敏度和BBPD性能。提出了一种基于折叠级联码的电荷泵（CP）来减小电荷延迟。采用0.18 μm CMOS技术制作了5g / 10g CDR原型，以证明所提出的技术在高数据速率/ ft应用中的有效性。所提出的CDR恢复数据的BER <；2.10 -13，仅产生1.04 ps RMS和7.5 ps峰值抖动。JTOL测试结果表明，所提出的CDR能够同时增强低频抖动跟踪和高频抖动滤波。CDR功耗为110.6 mW，其中环路增益自适应电路仅使用3.9 mW。
A Bang-Bang Clock and Data Recovery (CDR) with adaptive loop gain strategy is presented. The proposed strategy enhances CDR jitter performance even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode- based Charge Pump (CP) is proposed to minimize CP latency. The 5 G/10 G CDR prototype is fabricated in 0.18 μm CMOS technology to demonstrate the effectiveness of the proposed techniques for applications with high ratio of data-rate to ft. The proposed CDR recovers data with BER <; 2·10-13 and generates only 1.04 ps RMS and 7.5 ps peak-peak jitter. Jitter Tolerance (JTOL) test shows that the proposed CDR enhances low frequency jitter tracking and high frequency jitter filtering simultaneously for various jitter profiles. The CDR power consumption is 110.6 mW where only 3.9 mW is used for loop gain adaptation circuitry.