Three-dimensional integrated circuits
Three-dimensional integrated circuits
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DOI：
10.1147/rd.504.0491
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发表时间：
2006-07-01
影响因子：
1.3
通讯作者：
Ieong, M.
中科院分区：
文献类型：
--
作者：
Topol, A. W.;La Tulipe, D. C., Jr.;Ieong, M.
三维（3D）集成电路（ic）包含多层有源器件，具有显著提高芯片性能、功能和器件封装密度的潜力。它们还提供微芯片架构，并可促进异质材料、器件和信号的集成。然而，在实现这些优势之前，必须解决3D集成电路的关键技术挑战。更具体地说，构建具有多层有源器件的电路所需的工艺必须与当前最先进的硅加工技术兼容。这些工艺还必须显示出可制造性，即可靠性、良率、成熟度和合理的成本。为了满足这些需求，IBM推出了一种基于功能电路层转移的3D集成电路构建方案，并实现了许多工艺和设计创新。本文回顾了IBM为实现堆叠设备层的形成而开发的流程步骤和设计方面。提出了关于优化的层转移工艺的细节，包括以下描述：1)实现通过晶圆对准的玻璃基板工艺；2)氧化物熔合和圆片弯曲补偿方法，以提高键合时的对准公差；3)以及用于在两个堆叠器件层之间创建高纵横比（6:1 < AR < 11:1）触点的单大马士革图案和金属化方法。该工艺提供了堆叠层之间最短的距离（< 2 μ m），最高的互连密度(bbb10(8)通孔/cm(2))，以及极具侵略性的晶圆对晶圆排列（亚微米）能力。
Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods, for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers. This process provides the shortest distance between the stacked layers (< 2 mu m), the highest interconnection density (> 10(8) vias/cm(2)), and extremely aggressive wafer-to-wafer alignment (submicron) capability.