20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOS
20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOS
复制标题
0.13μm 数字 CMOS 中的 20 GHz 低功耗 QVCO 和去偏技术
DOI：
10.1109/cicc.2008.4672117
复制
发表时间：
2008
期刊：
影响因子：
--
通讯作者：
A. C. Carusone
中科院分区：
文献类型：
--
作者：
Masum Hossain;A. C. Carusone
提出了一种新的压控振荡器拓扑结构，将-gm振荡器的低功耗与Colpitts振荡器的固有缓冲相结合。利用这种拓扑结构，在0.13 μ m数字CMOS上实现了一个正交压控振荡器（QVCO），在20 GHz下消耗32 mW，调谐范围略高于10%。QVCO在20.17 GHz时的相位噪声测量值为-102.41 dBc/Hz。由于负载与油箱隔离，QVCO可以直接驱动50欧姆的阻抗或大容性负载，而无需额外缓冲。还提出了一种使用QVCO来调整时钟的技术，即QVCO接受20 mV的小转发时钟幅度，并提供200 mV的峰对峰差分时钟输出，在整个范围内（0-360度）进行相位线性控制。
A novel VCO topology is proposed that combines the low power of -gm oscillators with the inherent buffering of Colpitts oscillators. Using this topology, a quadrature VCO (QVCO) was implemented in 0.13 mum digital CMOS consuming 32 mW at 20 GHz with just over 10% tuning range. The measured phase noise of the QVCO at 20.17 GHz is -102.41 dBc/Hz at 1 MHz offset. Because the load is isolated from the tank, the QVCO can directly drive 50-Ohm impedances or large capacitive loads with no additional buffering. A technique to use the QVCO to deskew clocks is also presented whereby the QVCO accepts a small forwarded clock amplitude of 20 mV, and provides a 200 mV peak-to-peak differential clock output with linear control of the phase over the complete range, 0-360deg.