A 6-bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS
A 6-bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS
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DOI：
10.1109/tcsi.2011.2161368
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发表时间：
2009-06
期刊：
影响因子：
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通讯作者：
P. Nuzzo;C. Nani;C. Armiento;A. Sangiovanni-Vincentelli;J. Craninckx;G. V. D. Plas
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文献类型：
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作者：
P. Nuzzo;C. Nani;C. Armiento;A. Sangiovanni-Vincentelli;J. Craninckx;G. V. D. Plas
提出了一种阈值配置 SAR A/D 转换器，该转换器在运行时对其比较器阈值进行编程，以通过二分搜索近似输入信号。通过完全动态可配置比较器和异步控制器实现低功耗和小面积，无需基于电容器的反馈 D/A 转换器。采用 90 nm 数字 CMOS 技术的 6 位原型在 50 MS/s 的速度下实现了 32 dB SNDR，消耗 1 V 模拟和 0.7 V 数字电源的 240 μW 功率，即 150fJ/转换步，核心面积占用仅为 0.0055 mm2，比最先进的设计提高了 4 倍。
A threshold configuring SAR A/D converter is presented that programs its comparator threshold at runtime to approximate the input signal via binary search. Low power and small area are achieved via a fully dynamic configurable comparator and an asynchronous controller with no need for capacitor-based feedback D/A converter. A 6-bit prototype in 90-nm digital CMOS technology achieves 32-dB SNDR at 50 MS/s consuming 240 μW from 1-V analog and 0.7-V digital supplies, i.e. 150fJ/conversion-step, in a core area occupation of only 0.0055 mm2, a 4× improvement on state-of-the-art designs.