A Graph Reduction Approach to Symbolic Circuit Analysis

A Graph Reduction Approach to Symbolic Circuit Analysis
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DOI：
10.1109/aspdac.2007.357985
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发表时间：
2007-01
期刊：
2007 Asia and South Pacific Design Automation Conference
影响因子：
--
通讯作者：
G. Shi;Weiwei Chen;C. Shi
G. Shi;Weiwei Chen;C. Shi
中科院分区：
其他
文献类型：
--
作者：
G. Shi;Weiwei Chen;C. Shi

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A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed graph reduction process and a recursive sign determination algorithm. A symbolic analog circuit simulator is developed using a combination of these techniques. The simulator is able to analyze large analog circuits in the frequency domain. Experimental results are reported.