Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation
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Half-DRAM：来自细粒度激活重新思考的高带宽、低功耗DRAM架构
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
Yuan Xie
中科院分区：
文献类型：
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作者：
Zhang Tao;Ke Chen;Cong Xu;Guangyu Sun;Tao Wang;Yuan Xie
DRAM内存是现代计算系统总功耗的主要贡献者。因此，降低DRAM内存的功率对于提高系统级功率效率至关重要。已经提出了细颗粒的DRAM结构[1，2]，以降低激活/预声的功率。但是，那些先前的工作要么会导致大量的性能降解，要么引入大面积的头顶。在本文中，我们提出了一种新颖的记忆体系结构，其中的DRAM阵列进行了重组，以使一半的行被激活。半行激活可以有效地降低激活能力，同时维持一家银行可以提供的完整带宽。此外，半DRAM中的半行激活放松了DRAM的功率限制，并为进一步的绩效增长打开了机会。此外，可以通过集成子阵列级别并行性以提高记忆级并行性来并行发出两个半行访问。实验结果表明，使用微不足道的设计开销可以实现半DRAM的大幅提高和降低功率。
DRAM memory is a major contributor for the total power consumption in modern computing systems. Consequently, power reduction for DRAM memory is critical to improve system-level power efficiency. Fine-grained DRAM architecture [1, 2] has been proposed to reduce the activation/ precharge power. However, those prior work either incurs significant performance degradation or introduces large area overhead. In this paper, we propose a novel memory architecture Half-DRAM, in which the DRAM array is reorganized to enable only half of a row being activated. The half-row activation can effectively reduce activation power and meanwhile sustain the full bandwidth one bank can provide. In addition, the half-row activation in Half-DRAM relaxes the power constraint in DRAM, and opens up opportunities for further performance gain. Furthermore, two half-row accesses can be issued in parallel by integrating the sub-array level parallelism to improve the memory level parallelism. The experimental results show that Half-DRAM can achieve both significant performance improvement and power reduction, with negligible design overhead.