1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times
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DOI：
10.1109/vlsic.2012.6243782
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发表时间：
2012-06
期刊：
影响因子：
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通讯作者：
T. Ohsawa;H. Koike;S. Miura;H. Honjo;K. Tokutome;S. Ikeda;T. Hanyu;H. Ohno;T. Endoh
中科院分区：
文献类型：
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作者：
T. Ohsawa;H. Koike;S. Miura;H. Honjo;K. Tokutome;S. Ikeda;T. Hanyu;H. Ohno;T. Endoh
使用90nm CMOS和MTJ过程设计和制造的1MB非挥发性STT-RAM沿着单词线（WL）进行设计和制造。 /200PS分别降低操作功率并消除芯片的备用功率，以实验显示了用静态噪声缘（SNM）0.32V的数据，在VDD = 1V下。阵列访问时间为8NS，并在10NS周期下读取10.7MW的功率。
A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under Vdd=1V. The 1Mb chip with 2.19μm2 cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.