Voltage-induced degradation in self-aligned polycrystalline silicon gate n-type field-effect transistors with HfO2 gate dielectrics
Voltage-induced degradation in self-aligned polycrystalline silicon gate n-type field-effect transistors with HfO2 gate dielectrics
复制标题
采用 HfO2 栅极电介质的自对准多晶硅栅极 n 型场效应晶体管的电压引起的退化
DOI：
10.1063/1.1834992
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发表时间：
2004
影响因子：
4
通讯作者：
C. Hwang
中科院分区：
文献类型：
--
作者：
Jaehoon Park;Moonju Cho;Hong;T. Park;S. Lee;S. Hong;D. Jeong;Chihoon Lee;C. Hwang
本文研究了用原子层淀积HfO_2栅介质作为场效应晶体管的阈值电压的电压退化。在HfO2沉积之前，使用O3流对一些样品的Si沟道表面进行原位预处理，这形成了非常薄的SiO2界面层。这避免了在+3V栅极电压下的反型条件下阈值电压的移位高达1000s的应力时间。没有O3预处理的晶体管表现出严重的变化，在阈值电压的电子捕获。反向条件下的漏电流测量表明，漏电流不是控制退化的主要因素。相反，没有O3预处理的情况下，从硅低氧化物形成的界面陷阱似乎构成了降解的主要原因。
The voltage-induced degradation in the threshold voltage of field-effect transistors using atomic layer deposited HfO2-gate dielectrics was studied. Si channel surfaces of some samples were in situ pretreated using O3 flow before HfO2 deposition, which formed a very thin SiO2 interfacial layer. This avoided a shift of the threshold voltage up to a stress time of 1000s under inversion condition at +3V gate voltage. The transistors without O3 pretreatment showed a serious change in the threshold voltage by electron trapping. A leakage current measurement under inversion condition showed that the leakage current was not the major factor that controlled the degradation. Instead, the interfacial traps resulting from the Si suboxide formation for the cases without O3 pretreatment appeared to constitute the major reason for the degradation.