Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits
Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits
复制标题
基于符号多值运算电路的RSA加密处理器设计
DOI：
10.1002/scj.4690210603
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发表时间：
1990
期刊：
影响因子：
--
通讯作者：
T. Higuchi
中科院分区：
文献类型：
--
作者：
M. Kameyama;Shugang Wei;T. Higuchi
针对高速RSA公钥加密处理器，提出了一种面向LSI的基于带符号数（SD数）的多值硬件算法。在RSA加密处理中，需要一个很长的字长算法。该算法基于基数A SD数制，通过迭代加法实现了高速处理。加密处理器采用微程序控制。为了验证所提出的处理器架构的基本操作，使用二进制TTL逻辑IC实现了一个用于16位加密的模型处理器。本文用电子电路分析程序SPICE 2对2 μm CMOS加密大规模集成电路进行了模拟，并对模拟结果进行了综合评价。512位字长的消息的加密速率为60 kbit/s，这比相应的二进制LSI的加密速率快8倍。所开发的处理器包含约100 k晶体管，它可以在一个单一的单芯片上实现。
This paper proposes an LSI-oriented multiple-valued hardware algorithm based on the signed-digit number (SD number) for highspeed RSA public key encryption processor. A very long word-length arithmetic is required in RSA encryption processing. The proposed algorithm realizes a high-speed processing by iterative additions based on the radix-A SD number system. Microprogram control is adopted in the encryption processor. To verify the basic operation of the proposed processor architecture, a model processor for 16-bit encryption is implemented using binary TTL logic IC's. A comprehensive evaluation of the 2 μm CMOS encryption LSI is made by a simulation using the electronic circuit analysis program SPICE2. The encryption rate for the message of 512-bit word length is 60 kbit/s, which is a factor of eight times faster than that of the corresponding binary LSI. The developed processor contains about 100 k transistors and it can be implemented on a single single chip.