26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS
26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS
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26.4 具有 22nm CMOS 数字时钟校准功能的 25.6Gb/s 差分和 DDR4/GDDR5 双模发送器
DOI：
10.1109/isscc.2014.6757506
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
B. Casper
中科院分区：
文献类型：
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作者：
Tzu;G. Balamurugan;J. Jaussi;S. Hyvonen;J. Kennedy;Gokce Keskin;T. Musah;S. Shekhar;Rajesh Inti;Shreyas Sen;M. Mansuri;Clark Roberts;B. Casper
在当今的高速数字系统中存在各种各样的存储器配置，以满足特定于平台的带宽、功率、容量和成本限制。在短期内，DDR4和GDDR5有望满足服务器、客户端、图形和移动的平台的需求[1]。具有高速串行I/O增强功能的差分信号传输可能会继续为DDR4后和未来的缓冲内存解决方案提供I/O性能扩展。统一的内存接口可以满足所有这些内存标准的信令要求，提供了几个好处：降低成本和设计时间，更大的平台设计灵活性，以及从DDR4/GDDR5到高速差分内存接口的平滑过渡[2]。本文提出了一种支持单端1. 2 V-DDR4/1.5V-GDDR5（以下简称DDR模式）和高速差分信号（以下简称高速差分模式）的双模TX，该TX仅采用22 nm CMOS薄栅氧化层器件实现。其他关键设计特性包括：（a）仅使用有源器件实现的DDR4/GDDR5驱动器（无线性化电阻），（B）增强的电压模式驱动器电源调节，（c）支持两种TX模式下的预加重的可重新配置逻辑，以及（d）基于异步数字采样（ADS）的低开销数字时钟校准技术，以提高校准范围和精度。
A wide range of memory configurations exist in today's high-speed digital systems to meet platform-specific bandwidth, power, capacity, and cost constraints. In the near term, DDR4 and GDDR5 are expected to meet the needs of server, client, graphics and mobile platforms [1]. Differential signaling with high-speed serial I/O enhancements will potentially continue I/O performance scaling for post-DDR4 and future buffered memory solutions. A unified memory interface that can meet the signaling requirements of all these memory standards offers several benefits: reduced cost and design time, greater platform design flexibility, and a smoother transition from DDR4/GDDR5 to a high-speed differential memory interface [2]. This paper presents a dual-mode TX that supports single-ended (SE) 1.2V-DDR4/1.5V-GDDR5 (hereafter referred to as DDR-mode) as well as high-speed differential signaling (hereafter referred to as HSD-mode), which is implemented using only thin-gate-oxide devices in 22nm CMOS. Other key design features include: (a) a DDR4/GDDR5 driver implemented using only active devices (no linearizing resistors), (b) enhanced voltage-mode driver supply regulation, (c) reconfigurable logic to support pre-emphasis in both TX modes, and (d) low-overhead digital clock-calibration techniques based on asynchronous digital sampling (ADS) to improve calibration coverage and accuracy.