Alternative fabrication process for edgeless detectors on 6 in. wafers
Alternative fabrication process for edgeless detectors on 6 in. wafers
复制标题
6 英寸晶圆上无边缘探测器的替代制造工艺
DOI：
10.1016/j.nima.2010.06.119
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发表时间：
2011
影响因子：
1.4
通讯作者：
T. Virolainen
中科院分区：
文献类型：
--
作者：
J. Kalliopuska;S. Eränen;T. Virolainen
VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6in. (150mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150μm thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 5×5 and 1×1cm2edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.4×1.4cm2Medipix2 edgeless pixel detectors were also fabricated. This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100μm from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50–70nA/cm2and 580–660pF/cm2at, respectively, 40V reverse bias for the p-on-n. For the n-on-n design these parameters were 116–118nA/cm2and 930–960pF/cm2. The breakdown voltages were above 150V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13–28V.
