Estimating Operational Age of an Integrated Circuit
Estimating Operational Age of an Integrated Circuit
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DOI：
10.1007/s10836-021-05927-3
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发表时间：
2021-02
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影响因子：
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通讯作者：
Prattay Chowdhury;Ujjwal Guin;A. Singh;V. Agrawal
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作者：
Prattay Chowdhury;Ujjwal Guin;A. Singh;V. Agrawal
回收旧的集成电路作为新的替换部件来维护旧的电子系统是一个严重的可靠性问题。本文提出了一种新的方法来估计的工作年龄的CMOS芯片，通过测量IDDQ，静态电流从电源或总泄漏电流在稳态。该电流随着电路老化而减小，这主要是由于负偏置温度不稳定性（NBTI）引起的PMOS晶体管阈值电压的幅度的增加。我们利用NBTI对单个晶体管的影响取决于基于其ON状态的持续时间的操作应力的事实。我们的技术的新奇是一个归一化的差异，ΔI，计算从两个输入测试模式的电流测量，并提出作为一个自参考电路的年龄指标。选择第一种模式，使得其IDDQ由大量的最小应力PMOS晶体管控制;对于另一种模式，IDDQ由近似相等数量的高应力PMOS晶体管控制。这两个IDDQ值之间的差异随着电路年龄的增加而增加。这种方法不需要对电路进行硬件修改，因此可以应用于传统IC。模拟结果表明，我们可以可靠地识别使用时间短至6个月的回收IC。
Recycling of used ICs as new replacement parts in maintaining older electronic systems is a serious reliability concern. This paper presents a novel approach to estimate the operational age of CMOS chips by measuringIDDQ, the quiescent current from power supply or the total leakage current in steady state. This current decreases as the circuit ages, largely due to the increase in the magnitude of the PMOS transistor threshold voltage caused by negative bias temperature instability (NBTI). We exploit the fact that the impact of NBTI on an individual transistor depends upon the operational stress based upon the duration of its ON state. Novelty of our technique is a normalized difference, ΔI, computed from current measurements at two input test patterns and is proposed as a self referencing circuit age indicator. The first pattern is chosen such that itsIDDQis controlled by a large number of minimally stressed PMOS transistors; for the other theIDDQis controlled by approximately equal number of highly stressed PMOS transistors. The difference between these twoIDDQvalues increases with the circuit age. This approach requires no hardware modification in the circuit and, hence, can be applied to legacy ICs. Simulation results show that we can reliably identify recycled ICs that have been used for as little as six months.