Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits
Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits
复制标题
高密度 SRAM 和逻辑电路的基本阈值电压变化的影响
DOI：
10.1109/vlsit.1994.324400
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发表时间：
1994
期刊：
影响因子：
--
通讯作者：
K. Baker
中科院分区：
文献类型：
--
作者：
D. Burnett;K. Erington;Chitra K. Subramanian;K. Baker
随着电路上集成的晶体管数量不断增加，大约每18个月翻一番，晶体管变化对电路性能的影响变得更加显著。即使在没有系统变化的情况下(注入不均匀、Leff和Weff变化)，由于在极小的MOSFET沟道面积中掺杂原子的数量有限，阈值电压V/subT/也存在基本的变化。这项工作首次提出了这些基本的V/SUT/变化对SRAM单元稳定性和CMOS逻辑性能的影响。我们还分析了器件尺寸对这些V/B T/T变化的影响，并为未来的SRAM单元设计提出了指导方针。
As the number of transistors integrated on a circuit continues to increase, roughly doubling every 18 months, the impact of transistor variations on circuit performance becomes more significant. Even in the absence of systematic variations (implant nonuniformities, Leff and Weff variations), there exists a fundamental variability in the threshold voltage V/sub T/ due to the finite number of dopant atoms in the extremely small MOSFET channel area. This work presents for the first time the impact of these fundamental V/sub T/ variations on SRAM cell stability and CMOS logic performance. We also analyze the impact of device scaling on these V/sub T/ variations and propose guidelines for future SRAM cell design.<<ETX>>