Architecture of datapath-oriented coarse-grain logic and routing for FPGAs
Architecture of datapath-oriented coarse-grain logic and routing for FPGAs
复制标题
FPGA 面向数据路径的粗粒度逻辑和路由架构
DOI：
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发表时间：
2003
期刊：
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通讯作者：
L. David
中科院分区：
文献类型：
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作者：
A. Ye;Jonathan Rose;L. David
在本文中，我们提出一种新的面向数据路径的FPGA架构，利用粗粒度逻辑和路由资源来提高数据路径电路的面积效率。使用一组定制的面向数据路径的CAD工具和一组数据路径基准，我们研究了我们提出的体系结构的几个变体。我们发现，当总路由轨迹的40%到50%是粗粒度时，该架构实现了最高的区域效率。此外，与传统的FPGA架构相比，我们的面向数据路径的架构使用大约10%的面积来实现相同的电路。
In this paper, we propose a new datapath-oriented FPGA architecture that utilizes coarse-grain logic and routing resources to increase the area efficiency of datapath circuits. Using a set of custom-built datapath-oriented CAD tools and a set of datapath benchmarks, we investigated several variants of our proposed architecture. We found that the architecture achieves the highest area efficiency when 40% to 50% of the total routing tracks are coarse-grain. Furthermore, compared to conventional FPGA architectures, our datapath-oriented architecture uses about 10% less area to implement the same circuits.