Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique
Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique
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DOI：
10.1142/s0218126615500942
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发表时间：
2015-06
期刊：
影响因子：
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通讯作者：
Ji-zhong Shen;Liang Geng;Xue-Xiang Wu
中科院分区：
文献类型：
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作者：
Ji-zhong Shen;Liang Geng;Xue-Xiang Wu
触发器是数字集成电路中的一个重要单元，其特性对电路的性能有着深远的影响。为了降低触发器的功耗，提出了时钟触发沿控制技术，该技术可以在双边脉冲触发触发器（depff）中阻塞一个时钟周期中冗余的一个或两个触发沿。该技术可以在输入不变的情况下抑制冗余脉冲，消除所有冗余触发，减少触发器内部节点的冗余跃迁，从而降低功耗。然后提出了一种基于时钟触发边缘控制的DEPFF- cec技术。基于中芯国际65纳米工艺的布局后仿真结果表明，当输入开关活动度为10%时，所提出的DEPFF-CEC与同类器件相比，功耗提高了8.03-39.83%。因此，它适用于输入数据交换活动低的节能设计。
Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.