3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time
3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time
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3D-Wiz：一种新颖的高带宽、光学接口 3D DRAM 架构，可缩短随机访问时间
DOI：
10.1109/iccd.2014.6974654
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
S. Pasricha
中科院分区：
文献类型：
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作者：
Ishan G. Thakkar;S. Pasricha
本文介绍了3D-Wiz，这是一个高带宽，低延迟，光接口的3D DRAM架构与细粒度的数据组织和激活。3D-Wiz集成了数据阵列的子存储体级3D分区，以实现细粒度激活和更大的内存并行性。使用TSV和扇出缓冲器路由内部存储器总线的新方法使3D-Wiz能够使用较小尺寸的子阵列，而不会产生显著的面积开销。这又减少了随机存取等待时间和激活预充电能量。3D-Wiz的访问延迟为19.5ns，行周期时间为25 ns。其每次存取激活能和预充电能分别为0.78nJ和0.62nJ，面积效率为42.5%。3D-Wiz在其他知名的3D DRAM架构中产生最佳的每次访问延迟和能耗值。PARSEC基准测试的实验结果表明，3D-Wiz实现了38.8%的性能提高，81.1%的功耗降低，和77.1%的能量延迟产品（EDP）平均减少3D DRAM架构从以前的工作。
This paper introduces 3D-Wiz, which is a high bandwidth, low latency, optically interfaced 3D DRAM architecture with fine grained data organization and activation. 3D-Wiz integrates sub-bank level 3D partitioning of the data array to enable fine-grained activation and greater memory parallelism. A novel method of routing the internal memory bus using TSVs and fan-out buffers enables 3D-Wiz to use smaller dimension subarrays without significant area overhead. This in turn reduces the random access latency and activation-precharge energy. 3D-Wiz demonstrates access latency of 19.5ns and row cycle time of 25ns. It yields per access activation energy and precharge energy of 0.78nJ and 0.62nJ respectively with 42.5% area efficiency. 3D-Wiz yields the best latency and energy consumption values per access among other well-known 3D DRAM architectures. Experimental results with PARSEC benchmarks indicate that 3D-Wiz achieves 38.8% improvement in performance, 81.1% reduction in power consumption, and 77.1% reduction in energy-delay product (EDP) on average over 3D DRAM architectures from prior work.