Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells
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DOI：
10.1016/j.mejo.2013.10.013
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发表时间：
2014-02-01
影响因子：
2.2
通讯作者：
Olivieri, Mauro
中科院分区：
文献类型：
--
作者：
Abbas, Zia;Olivieri, Mauro
泄漏估计是纳米级技术数字设计流的重要一步。尽管在独立设备和电路中具有散装CMOS技术扩展的泄漏趋势上存在可靠的数据，但缺乏公共领域的结果，结果对整个标准单元组的缩放量表对泄漏功耗的影响。我们对使用逻辑级估计模型的标准单元格库进行了分析，该模型得到了Spice BSIM4比较支持。 SPICE上的逻辑级模型加速度为> 10（3），平均精度低于1％的误差。因此，我们探讨了相对于不同的泄漏机制（子阈值，身体，门）和输入模式依赖性的缩放对整个标准单元组的影响。尽管身体泄漏似乎是占主导地位的，但预计阈值泄漏的增加将比其他缩放率增加更多。据报道，整个分析的详细数据用于进一步研究泄漏意识到的数字设计。 （c）2013 Elsevier Ltd.保留所有权利。
Leakage estimation is an important step in nano-scale technology digital design flows. While reliable data exist on leakage trends with bulk CMOS technology scaling in stand-alone devices and circuits, there is a lack of public domain results on the effect of scaling on leakage power consumption for a complete standard cell set. We present an analysis on a standard cell library applying a logic-level estimation model, supported by SPICE BSIM4 comparison. The logic-level model speedup over SPICE is > 10(3) with average accuracy below 1% error. We therefore explore the effects of scaling on the whole standard cell set with respect to different leakage mechanisms (sub-threshold, body, gate) and to input pattern dependence. While body leakage appears to be dominant, sub-threshold leakage is expected to increase more than other components with scaling. Detailed data of the whole analysis are reported for use in further research on leakage aware digital design. (C) 2013 Elsevier Ltd. All rights reserved.