Efficient Decoder Implementation for QC-LDPC Codes
Efficient Decoder Implementation for QC-LDPC Codes
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DOI：
10.1109/icccas.2006.285182
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发表时间：
2006-06
期刊：
影响因子：
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通讯作者：
Jin Sha;M. Gao;Zhongjin Zhang;Li Li-Li;Zhongfeng Wang
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文献类型：
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作者：
Jin Sha;M. Gao;Zhongjin Zhang;Li Li-Li;Zhongfeng Wang
通道编码是通信系统中的重要组成部分。低密度平价检查代码是一种在下一代行业标准中考虑的突出错误纠正代码。本文介绍了使用改良的MIN-SUM解码算法适用于准环境低密度奇偶校验检查代码的非常高速解码器结构。通常，大约70％的消息内存可以保存在传统的解码器体系结构上，并且由于高效的VLSI体系结构，可以在很大程度上加速解码速度。因此，提出的方法促进了LDPC代码在区域/延迟敏感通信系统中的应用。
Channel coding is an important building block in communication systems. Low-density parity-check codes is one kind of prominent error correcting codes being considered in next generation industry standards. This paper presents a memory efficient, very high speed decoder architecture suited for quasi-cyclic low-density parity-check codes using modified Min-Sum decoding algorithm. In general, about seventy percent of message memory can be saved over conventional decoder architectures, and the decoding speed can be largely accelerated because of the highly efficient VLSI architecture. Consequently, the proposed approach facilitates the applications of LDPC codes in area/latency sensitive communication systems.