A Low-Power Capacitive Charge Pump Based Pipelined ADC
A Low-Power Capacitive Charge Pump Based Pipelined ADC
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DOI：
10.1109/jssc.2010.2042524
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发表时间：
2010-04
影响因子：
5.4
通讯作者：
I. Ahmed;J. Mulder;D. Johns
中科院分区：
文献类型：
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作者：
I. Ahmed;J. Mulder;D. Johns
提出了一种低功耗流水线ADC拓扑结构，该拓扑结构使用容性电荷泵、源极跟随器和数字校准来消除高功耗运算放大器的需求，从而在流水线ADC中实现良好的线性度。差分电荷泵技术实现了>10位线性度，并且不需要显式共模反馈电路。该ADC采用1.8 V、0.18 μ m CMOS工艺设计，工作速度为50 MS/s，实测结果显示，ADC的峰值SNDR和SFDR分别为58.2 dB（9.4 ENOB）和66 dB。ADC的所有有源电路功耗为3.9 mW，所有时钟和数字电路功耗为6 mW。
A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves >10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 ¿m CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits.