29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic
29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic
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29.3 使用单通量量子逻辑的 48GHz 5.6mW 门级流水线乘法器
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
A. Fujimaki
中科院分区：
文献类型：
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作者：
Ikki Nagaoka;Masamitsu Tanaka;Koji Inoue;A. Fujimaki
基于超导单通量量子逻辑的乘法器在48 GHz频率下工作，实测功耗为5.6mW。乘数执行8美元 在每个时钟周期进行8倍的有符号乘法。该设计是基于位并行，门级流水线结构，最终利用SFQ逻辑的高吞吐量性能。测试芯片采用1.0 μ m9层工艺制造，由20，251个Nb/AlOx/Nb约瑟夫森结（JJ）组成。通过片上高速测试验证了运算的正确性。
A multiplier based on superconductor single-flux-quantum (SFQ) logic is demonstrated up to 48GHz with the measured power consumption of 5.6 mW. The multiplier performs $8 imes 8 -$ bit signed multiplication every clock cycle. The design is based on a bit-parallel, gate-level-pipelined structure that exploits ultimately high-throughput performance of SFQ logic. The test chip fabricated using a $1.0- mu mathrm {m}$, 9-layer process consists of 20,251 Nb/AlOx/Nb Josephson junctions (JJs). The correctness of operation is verified by on-chip high-speed testing.