A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration
A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration
复制标题
FPGA 上使用动态重配置的高分辨率时间数字转换器
DOI：
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发表时间：
2011
影响因子：
5.6
通讯作者：
J. David
中科院分区：
文献类型：
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作者：
Marc;J. David
提出了一种适用于支持动态重构的现场可编程门阵列的高精度、高精度时间-数字转换器(TDC)结构。所提出的体系结构依赖于由路由交换结构内的可编程互联点实现的多个并行高分辨率延迟线。这些延迟线的分辨率为1-ps，范围为3 ns。提出了一种考虑工艺-电压-温度变化和时钟偏差的校准过程。一个分辨率为50ps、精度高达35ps的TDC已在Virtex-II Pro现场可编程门阵列上实现。结果表明，所提出的结构和校准过程可以实现高达10ps的分辨率。
A high-resolution high-precision time-to-digital converter (TDC) architecture is presented for implementation on field-programmable gate arrays (FPGAs) supporting dynamic reconfiguration. The proposed architecture relies on multiple parallel high-resolution delay lines implemented by the programmable interconnection points within the routing switch fabric. These delay lines feature a 1-ps resolution over a range of 3 ns. A calibration process is proposed to take process-voltage-temperature variations, as well as clock skew, into account. A TDC with a 50-ps resolution and precision as high as 35 ps has been implemented on a Virtex-II Pro FPGA. Results show that the proposed architecture and calibration process can be used to achieve resolutions as fine as 10 ps.