Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications
Scalability of Sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications
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DOI：
10.1109/ted.2010.2049075
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发表时间：
2010-06
影响因子：
3.1
通讯作者：
Daehyun Kim;J. D. del Alamo
中科院分区：
文献类型：
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作者：
Daehyun Kim;J. D. del Alamo
我们从逻辑操作的角度对InP衬底上亚100 nm InAs高电子迁移率晶体管（HEMT）的标度行为进行了实验研究。这些设备已被设计为可扩展性和联合收割机结合薄InAlAs屏障和包含纯InAs子通道的薄通道。栅极长度低至40 nm的InAs HEMT表现出优异的逻辑品质因数，例如ION/IOFF = 9 × 104，漏致势垒降低= 80 mV/V，S = 70 mV/dec，以及在VDS = 0.5 V时估计的0.6 ps的逻辑门延迟。此外，我们还获得了Lg = 40 nm的优异高频操作，如fT = 491 GHz和fmax = 402 GHz，在VDS = 0.5 V。尽管InAs子沟道的窄带隙，在所研究的条件下，我们的器件被证明不会遭受过度的带间隧穿。以最先进的Si器件为基准，40 nm InAs HEMT在ILeak = 200 nA/μm时的ION = 0.6 A/μ m。这比最先进的高性能65 nm nMOSFET高出约两倍，具有相当的物理栅极长度和ILeak。
We have experimentally studied the scaling behavior of sub-100-nm InAs high-electron mobility transistors (HEMTs) on InP substrate from the logic operation point of view. These devices have been designed for scalability and combine a thin InAlAs barrier and a thin channel containing a pure InAs subchannel. InAs HEMTs with gate length down to 40 nm exhibit excellent logic figures of merit, such as ION/IOFF = 9 × 104, drain-induced-barrier lowering = 80 mV/V, S = 70 mV/dec, and an estimated logic gate delay of 0.6 ps at VDS = 0.5 V. In addition, we have obtained excellent high-frequency operation with Lg = 40 nm, such as fT = 491 GHz and fmax = 402 GHz at VDS = 0.5 V. In spite of the narrow bandgap of InAs subchannel, under the studied conditions, our devices are shown not to suffer from excessive band-to-band tunneling. When benchmarked against state-of-the-art Si devices, 40-nm InAs HEMTs exhibit ION = 0.6 A/μm at ILeak = 200 nA/μm. This is about two times higher ION than state-of-the-art high-performance 65-nm nMOSFET with comparable physical gate length and ILeak.