Modeling and testing of interference faults in the nano NAND Flash memory
Modeling and testing of interference faults in the nano NAND Flash memory
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纳米NAND闪存干扰故障的建模与测试
DOI：
10.5555/2492708.2492839
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发表时间：
2012
期刊：
影响因子：
--
通讯作者：
Chung Len Lee
中科院分区：
文献类型：
--
作者：
Jin Zha;Xiaole Cui;Chung Len Lee
制造技术的进步提高了NAND闪存的尺寸和密度，但也带来了新类型的缺陷，需要进行测试以考虑质量。本文基于电路级仿真分析了深纳米NAND Flash存储器的三种物理缺陷，并提出了新的干扰故障类别。最后给出了最坏情况下的故障检测算法。该算法除了测试IF外，还可以检测NAND Flash的常规地址故障、干扰故障和其他RAM类故障。
Advance of the fabrication technology has enhanced the size and density for the NAND Flash memory but also brought new types of defects which need to be tested for the quality consideration. This work analyzes three types of physical defects for the deep nano-meter NAND Flash memory based on the circuit level simulation and proposes new categories of interference faults (IFs). Testing algorithm is also proposed to test the faults under the worst case condition. The algorithm, in addition to test IFs, can also detect the conventional address faults, disturbance faults and other RAM-like faults for the NAND Flash.