Understanding the feasibility of scaled III–V TFET for logic by bridging atomistic simulations and experimental results
Understanding the feasibility of scaled III–V TFET for logic by bridging atomistic simulations and experimental results
复制标题
通过连接原子模拟和实验结果，了解逻辑缩放 III-V TFET 的可行性
DOI：
10.1109/vlsit.2012.6242522
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发表时间：
2012
期刊：
影响因子：
--
通讯作者：
I. Young
中科院分区：
文献类型：
--
作者：
U. Avci;S. Hasan;D. Nikonov;R. Rios;K. Kuhn;I. Young
III-V TFET的实验特性和原子量子力学预测之间的详细比较，研究的有效性的缩放TFET的性能改善的预测。模拟没有采用任何拟合参数来匹配实验数据，而是使用材料和几何参数作为唯一的输入。结果表明，实验和模拟特性基本一致，表明实验装置没有明显的未知效应或缺陷，原子模拟具有较好的可预测性。缩放TFET预测和大型实验TFET器件之间的差异被证明是由于几何形状，这意味着改进的静电与薄体和双栅极（DG）的TFET缩放。结果表明，III-V TFET是未来低电压逻辑应用的现实候选者。
A detailed comparison between III-V TFET's experimental characteristics and atomistic quantum mechanical predictions is reported to study the validity of the performance improvement predictions of a scaled TFET. Simulations did not employ any fitting parameters to match the experimental data, but instead used material and geometry parameters as the only inputs. The results show that the experimental and simulation characteristics are in reasonable agreement, suggesting that the experimental devices are without significant unknown effects or defects, and the atomistic simulations have good predictability. The differences between scaled TFET predictions and large experimental TFET devices are shown to be due to the geometry, meaning that improved electrostatics with thin body and double-gate (DG) is required for TFET scaling. Results demonstrate that the III-V TFET is a realistic candidate for future low-voltage logic applications.