Quantitative analysis of Control Flow Checking mechanisms for soft errors

Quantitative analysis of Control Flow Checking mechanisms for soft errors
复制标题

软错误控制流检查机制的定量分析

DOI:
--
复制
发表时间:
2014
期刊:
Design Automation Conference
影响因子:
--
通讯作者:
Carole
Carole
中科院分区:
--
文献类型:
--
作者:
Aviral Shrivastava;Abhishek Rhisheekesan;Reiley Jeyapaul;Carole

文献摘要

被引文献

相似文献

基于控制流检查(CFC)的技术已经获得了提供有效的、低开销的软错误保护的声誉。其基本思想是,如果控制流-或执行的指令序列-是正确的,那么很可能程序的执行是正确的。尽管研究人员声称拟议的CFC技术的有效性,但我们认为他们的评估还不充分,甚至可能是错误的!最近,已经提出了脆弱性度量来量化计算对软错误的敏感性。在此基础上,我们对现有的几种CFC方案的有效性进行了定量评估,并得到了令人惊讶的结果。我们的研究结果表明,现有的CFC技术不仅是无效的,在保护计算软错误,但它们会产生额外的功率和性能开销。纯软件氟氯化碳保护计划(CFCSS [14]、CFCSS+NA [2]和CEDA [18])增加了18%至21%的系统脆弱性,性能开销为17%至38%;混合CFC保护技术,CFEDC [4]也增加了5%的脆弱性;虽然对于仅硬件CFC保护技术CFCET [15],漏洞几乎保持相同,但它们导致设计成本、面积以及由于其实现所需的硬件修改而导致的功率。
Control Flow Checking (CFC) based techniques have gained a reputation of providing effective, yet low-overhead protection from soft errors. The basic idea is that if the control flow - or the sequence of instructions that are executed - is correct, then most probably the execution of the program is correct. Although researchers claim the effectiveness of the proposed CFC techniques, we argue that their evaluation has been inadequate and can even be wrong! Recently, the metric of vulnerability has been proposed to quantify the susceptibility of computation to soft errors. Laced with this comprehensive metric, we quantitatively evaluate the effectiveness of several existing CFC schemes, and obtain surprising results. Our results show that existing CFC techniques are not only ineffective in protecting computation from soft errors, but that they incur additional power and performance overheads. Software-only CFC protection schemes (CFCSS [14], CFCSS+NA [2], and CEDA [18]) increase system vulnerability by 18% to 21% with 17% to 38% performance overhead; Hybrid CFC protection technique, CFEDC [4] also increases the vulnerability by 5%; While the vulnerability remains almost the same for hardware only CFC protection technique, CFCET [15], they cause overheads of design cost, area, and power due to the hardware modifications required for their implementations.